clk_counter.v.bak

来自「该代码中有不少关于学习verilog HDL的例子,对初学者有帮助」· BAK 代码 · 共 9 行

module clk_counter(count_out,clk);
output count_out;
input clk;
reg[3:0] count_out;
initial
  count_out=0;
always@(posedge clk)
  count_out=count_out+1;
endmodule