mytest.v.bak

来自「该代码中有不少关于学习verilog HDL的例子,对初学者有帮助」· BAK 代码 · 共 15 行

module mytest;
integer a,b;
initial
  fork
    a=3;
    b=2;
    forever fork
      #5 a<=a+1;
      #5 b<=a;
    join
  join
initial begin
  $monitor($time,"a=%d,b=%d",a,b);
end
endmodule