ex4.v

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module ex4;
reg a,b,c;
initial  
  fork
    a=0;b=1;c=0;
    #5 c<=b;
    #5 b<=a;
  join
initial
    $monitor($time,,,,"a=%b,b=%b,c=%b",a,b,c);
endmodule