connect_test.v

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module connect_test;
reg a;
reg[3:0] b;
reg[5:0] c;
initial
  begin
    a=1;
    b=4;
    c=6;
    $display("{a,b} is %b",{a,b});
    $display("{b,c} is %b",{b,c});
    $display("{b,c,{4{a}}} is %b",{b,c,{4{a}}});
  end
endmodule