counter.v

来自「该代码中有不少关于学习verilog HDL的例子,对初学者有帮助」· Verilog 代码 · 共 12 行

module counter;
integer count;
initial
  begin
    count=0;
    while(count<=100)
      begin
        $display("count is %d",count);
        count=count+1;
      end 
  end
endmodule