unknown.v.bak

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module unknown;
initial
$display("I am a postgraduate of Xidian University!");
reg[10*16:0] a;
initial
  begin
    a="I am a hansome man!";
    $display("%S",a);
    $display("%s is equal to %b",a,a);
    $displayh(a);
    $displayb(a);
    $displayb("%s",a);
    $displayh("%s",a);
    $displayb("I am a hansome man!");
    $displayh("I am a hansome man!");
    $displayb("a=",a);
    $displayh("a=",a);
    $displayb("",a);     //default between double quotation mark is licit
    $displayb("",a);     // be similar to  the above
    $displayb(" ",a);    //space can be embedded
    $displayh(" ",a);    //space can be embedded
  end
endmodule