shift_register_3.v.bak

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module shift_register_3(d_out,reg_a,reg_b,d_in,clk);
output d_out,reg_a,reg_b;
input d_in,clk;
reg d_out,reg_a,reg_b;
always@(posedge clk)
  begin
    d_out=reg_b;
    reg_b=reg_a;
    reg_a=d_in;
  end
endmodule


module shift_register_3_test();
reg d_in,clk;
shift_register_3 M1(d_out,d_in,clk);
initial
  begin
    d_in=0;clk=0;
    #10 d_in=1;
    #10 clk=0;
    #10 d_in=0;
    #10 clk=1;
    #10 d_in=0;clk=1;
    #10 d_in=1;clk=0;
    #10 d_in=1;clk=1;
    #10 d_in=0;clk=0;
    #10 d_in=0;clk=1;
  end
endmodule