binaryto3digit.vhd

2个4位二进制数相加的加法器件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity binaryto3digit is
  port(SW : in std_logic_vector(17 downto 0);
       HEX0,HEX1,HEX2,HEX4,HEX5,HEX6,HEX7 : out std_logic_vector(6 downto 0));
end;

architecture bhv of binaryto3digit is
  component binarytodigit is
    port (lowfirst,lowsecond,highfirst,highsecond : in std_logic_vector(3 downto 0);
          inofout : in std_logic;
          lowout : out std_logic_vector(3 downto 0);
          highout : out std_logic_vector(4 downto 0));
  end component;

  component circuitB is
    port (come : in std_logic;
          tosegment : out std_logic_vector(3 downto 0));
  end component;
  
  component seven_segment is 
    port (c : in std_logic_vector(3 downto 0);
          show : out std_logic_vector(6 downto 0));
  end component;

  signal numline : std_logic_vector(16 downto 0);
  signal lowtoseg,hightoseg : std_logic_vector(3 downto 0);
  signal hightoB : std_logic;
  signal Btoseg : std_logic_vector(3 downto 0);

  begin
    numline(16 downto 0)<=SW(16 downto 0);
    u1 : binarytodigit port map (highfirst=>numline(15 downto 12),
                                 lowfirst=>numline(11 downto 8),
                                 highsecond=>numline(7 downto 4),
                                 lowsecond=>numline(3 downto 0),
                                 inofout=>numline(16),
                                 lowout=>lowtoseg,
                                 highout(3 downto 0)=>hightoseg,
                                 highout(4)=>hightoB);

    u2 : circuitB port map(come=>hightoB,
                           tosegment=>Btoseg);
  
    u3 : seven_segment port map (c=>numline(15 downto 12),
                                 show=>HEX7);
   
    u4 : seven_segment port map (c=>numline(11 downto 8),
                                 show=>HEX6);

    u5 : seven_segment port map (c=>numline(7 downto 4),
                                 show=>HEX5);

    u6 : seven_segment port map (c=>numline(3 downto 0),
                                 show=>HEX4);

    u7 : seven_segment port map (c=>hightoseg,
                                 show=>HEX1);

    u8 : seven_segment port map (c=>lowtoseg,
                                 show=>HEX0);
    
    u9 : seven_segment port map (c=>Btoseg,
                                 show=>HEX2);
end architecture;