seven_segment.vhd

来自「2个4位二进制数相加的加法器件」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity seven_segment is
  port (c : in std_logic_vector(3 downto 0);
        show : out std_logic_vector(6 downto 0));
end;

architecture bhv of seven_segment is 
  begin
    process(c)
      begin
        case c is
          when "0000" => show<="1000000";
          when "0001" => show<="1111001";
          when "0010" => show<="0100100";
          when "0011" => show<="0110000";
          when "0100" => show<="0011001";
          when "0101" => show<="0010010";
          when "0110" => show<="0000010";
          when "0111" => show<="1111000";
          when "1000" => show<="0000000";
          when "1001" => show<="0010000";
          when "1010" => show<="0001000";
          when "1011" => show<="0000011";
          when "1100" => show<="1000110";
          when "1101" => show<="0100001";
          when "1110" => show<="0000110";
          when "1111" => show<="0001110";
          when others => null;
        end case;
    end process;
end architecture;