addandconvert.vhd

来自「2个4位二进制数相加的加法器件」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity addandconvert is
  port (num1,num2 : in std_logic_vector(3 downto 0);
         carry_in : in std_logic;
        carry_out : out std_logic_vector(4 downto 0));
end;

architecture one of addandconvert is
  component part3
  port (a,b : in std_logic_vector(3 downto 0);
          s : out std_logic_vector(3 downto 0);
     output : out std_logic;
        cin : in std_logic);
  end component;
  
  component complete
    port (v : in std_logic_vector(4 downto 0);
          m : out std_logic_vector(4 downto 0));
  end component;
  
  signal sum : std_logic_vector(3 downto 0);
  signal sum_out : std_logic;

  begin
  u1 : part3 port map (cin=>carry_in,
                         a=>num1,
                         b=>num2,
                         s=>sum,
                    output=>sum_out);
  u2 : complete port map (v(3 downto 0)=>sum,
                          v(4)=>sum_out,
                          m=>carry_out(4 downto 0));
end architecture;