full_adder.vhd

来自「2个4位二进制数相加的加法器件」· VHDL 代码 · 共 65 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity full_adder is
  port (ain,bin : in std_logic;
         ci : in std_logic;
          s : out std_logic;
         cout : out std_logic);
end;

architecture one of full_adder is
  component half_adder 
    port (a,b : in std_logic;
        co,so : out std_logic);
  end component;

  component or2b
    port (a,b : in std_logic;
            c : out std_logic);
  end component;
  signal d,e,f : std_logic;
    begin 
      u1 : half_adder port map(a=>ain,
                               b=>bin,
                               co=>d,
                               so=>e);
      u2 : half_adder port map(a=>e,
                               b=>ci,
                               co=>f,
                               so=>s);
      u3 : or2b port map(a=>d,
                        b=>f,
                        c=>cout);
end architecture one;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity half_adder is 
  port (a,b : in std_logic;
      co,so : out std_logic);
end;

architecture fh of half_adder is
  begin
    so <= not(a xor (not b));
    co <= a and b;
end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity or2b is
  port (a,b : in std_logic;
          c : out std_logic);
end;

architecture two of or2b is
  begin 
    c <= a or b;
end architecture;