binarytodigit.vhd

来自「2个4位二进制数相加的加法器件」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity binarytodigit is
  port (lowfirst,lowsecond,highfirst,highsecond : in std_logic_vector(3 downto 0);
                                        inofout : in std_logic;
                                         lowout : out std_logic_vector(3 downto 0);
                                        highout : out std_logic_vector(4 downto 0));
end;

architecture goodtaste of binarytodigit is
  component addandconvert is
    port (num1,num2 : in std_logic_vector(3 downto 0);
           carry_in : in std_logic;
          carry_out : out std_logic_vector(4 downto 0));
  end component;

  signal carry : std_logic;

  begin
    convert1 : addandconvert port map (num1=>lowfirst,
                                       num2=>lowsecond,
                                       carry_in=>inofout,
                                       carry_out(3 downto 0)=>lowout,
                                       carry_out(4)=>carry);
    convert2 : addandconvert port map (num1=>highfirst,
                                       num2=>highsecond,
                                       carry_in=>carry,
                                       carry_out(4 downto 0)=>highout);
end architecture;