complete.vhd

2个4位二进制数相加的加法器件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity complete is
  port (v : in std_logic_vector(4 downto 0);
        m : out std_logic_vector(4 downto 0));
end entity;

architecture name of complete is
  component mux21 is
    port (a,b : in std_logic;
            s : in std_logic;
            q : out std_logic);
  end component;
  
  component compare is 
    port (v5 : in std_logic_vector(4 downto 0);
           z : out std_logic);
  end component;
  
  component convert is
    port (v4 : in std_logic_vector(3 downto 0);
         con : out std_logic_vector(3 downto 0));
  end component;

  signal e : std_logic_vector(4 downto 0);
  signal b : std_logic_vector(3 downto 0);
  signal c : std_logic;
  constant mux : std_logic := '0';

    begin
      e<= v;      
      u1 : compare port map(v5(4)=>e(4),
                            v5(3)=>e(3),
                            v5(2)=>e(2),
                            v5(1)=>e(1),
                            v5(0)=>e(0),
                                  z=>c);
      u2 : convert port map(v4(3)=>e(3),
                            v4(2)=>e(2),
                            v4(1)=>e(1),
                            v4(0)=>e(0),
                           con(3)=>b(3),
                           con(2)=>b(2),
                           con(1)=>b(1),
                           con(0)=>b(0));
      u3 : mux21 port map (a=>e(0),
                           b=>b(0),
                           s=>c,
                           q=>m(0));
      u4 : mux21 port map (a=>e(1),
                           b=>b(1),
                           s=>c,
                           q=>m(1));
      u5 : mux21 port map (a=>e(2),
                           b=>b(2),
                           s=>c,
                           q=>m(2));
      u6 : mux21 port map (a=>e(3),
                           b=>b(3),
                           s=>c,
                           q=>m(3));
      m(4)<= c;

end name;

 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity mux21 is
  port (a,b : in std_logic;
        s : in bit;
        q : out std_logic);
end;

architecture rifi of mux21 is
  begin
    q <= a when s = '0' else b;
end rifi;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity compare is
  port (v5 : in std_logic_vector(4 downto 0);
         z : out std_logic);
end;

architecture like of compare is
  begin
    z<='1' when (v5>="01010") and (v5<"10100") else '0';
end architecture like;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity convert is
  port (v4 : in std_logic_vector(3 downto 0);
       con : out std_logic_vector(3 downto 0));
end;

architecture fact of convert is
  begin 
    con <= v4 + "0110";
    
end architecture fact;