circuitb.vhd

2个4位二进制数相加的加法器件

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity circuitB is 
  port (come : in std_logic;
        tosegment : out std_logic_vector(3 downto 0));
end;

architecture bhv of circuitB is 
  begin
    tosegment<="0001" when come='1' else "0000";
end;