part3.vhd

来自「2个4位二进制数相加的加法器件」· VHDL 代码 · 共 41 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity part3 is 
  port (a,b : in std_logic_vector(3 downto 0);
          s : out std_logic_vector(3 downto 0);
     output : out std_logic;
        cin : in std_logic);
end;

architecture bit_adder of part3 is
  component full_adder
    port (ain,bin : in std_logic;
               ci : in std_logic;
                s : out std_logic;
             cout : out std_logic);
  end component;
  signal d,e,f : std_logic;
    begin
      u1 : full_adder port map (ain=>a(0),
                                bin=>b(0),
                                 ci=>cin,
                                  s=>s(0),
                               cout=>d);
      u2 : full_adder port map (ain=>a(1),
                                bin=>b(1),
                                 ci=>d,
                                  s=>s(1),
                               cout=>e);
      u3 : full_adder port map (ain=>a(2),
                                bin=>b(2),
                                 ci=>e,
                                  s=>s(2),
                               cout=>f);
      u4 : full_adder port map (ain=>a(3),
                                bin=>b(3),
                                 ci=>f,
                                  s=>s(3),
                               cout=>output);
end architecture ;