ksubabs.vhd

使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ksubabs IS 
   PORT 
       ( ABSXY,K: IN STD_LOGIC_VECTOR(6 DOWNTO 0);
                 SOUT : OUT STD_LOGIC;
         jiashu : OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );
END ;
ARCHITECTURE HDLARCH OF ksubabs IS
COMPONENT SUBER
   PORT (X,Y,SUB_IN : IN STD_LOGIC;
         DIFFR,SUB_OUT : OUT STD_LOGIC);
END COMPONENT;
SIGNAL STMP : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN 
STMP(0)<='0';SOUT<=STMP(7);
GENSUB :FOR I IN 0 TO 6 GENERATE
U1 : SUBER PORT MAP(X=>k(I),Y=>absxy(I),SUB_IN =>STMP(I),DIFFR=>jiashu(I),SUB_OUT=>STMP(I+1));
END GENERATE;
END;