log_map_chip2.vhd

使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY LOG_MAP_CHIP2 IS
   PORT(  CLK,RESET,SET:IN STD_LOGIC;
            ADIN : STD_LOGIC_VECTOR(7 DOWNTO 0);
         R0,R1,R2,R3 : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
               KIN  : IN STD_LOGIC_VECTOR(6 DOWNTO 0) ;
         KNAIN0,KNAIN1,KNAIN2,KNAIN3,KNAIN4,KNAIN5,KNAIN6,KNAIN7 : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)    
   );
END;

ARCHITECTURE BEHV OF LOG_MAP_CHIP2 IS

COMPONENT MAXSTARTXT IS 
     PORT(   XIN,YIN : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
             KIN :IN STD_LOGIC_VECTOR(6 DOWNTO 0);
             SOUTPUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT ADD8 IS 
   PORT 
       ( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 C : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) );
END COMPONENT;

COMPONENT COMPARE IS
   PORT(AIN0,AIN1,AIN2,AIN3,AIN4,AIN5,AIN6,AIN7 : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
          AOUT : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
   );
END COMPONENT;

COMPONENT JIAN8 IS 
   PORT 
       ( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
          C : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END COMPONENT;

COMPONENT ram_chip2 IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		we		: IN STD_LOGIC  := '1';
		data		: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
	);
END COMPONENT;

COMPONENT CONTROL IS
   PORT( CLK,RESET,SET : IN STD_LOGIC;
         ADIN  : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
         ADOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
         WR  : OUT STD_LOGIC );
END COMPONENT;


COMPONENT FENXIN1 IS 
   PORT 
       ( DATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
         NAIN0,NAIN1,NAIN2,NAIN3,NAIN4,NAIN5,NAIN6,NAIN7 : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0));      
END COMPONENT;

COMPONENT FENXIN2 IS 
   PORT 
       ( DATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
         NAIN0,NAIN1,NAIN2,NAIN3,NAIN4,NAIN5,NAIN6,NAIN7 : IN  STD_LOGIC_VECTOR(7 DOWNTO 0));      
END COMPONENT;


SIGNAL STMP1,STMP2,STMP3,STMP4,STMP5,STMP6,STMP7,STMP8,STMP9,STMP10,STMP11,STMP12,STMP13,STMP14,STMP15,STMP16 : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL NIN0,NIN1,NIN2,NIN3,NIN4,NIN5,NIN6,NIN7,LINSHI :   STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LINEWR : STD_LOGIC;
SIGNAL AIN0,AIN1,AIN2,AIN3,AIN4,AIN5,AIN6,AIN7 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LINEADOUT :STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LINEDATA,LINEQ :		 STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL LINEAIN0,LINEAIN1,LINEAIN2,LINEAIN3,LINEAIN4,LINEAIN5,LINEAIN6,LINEAIN7 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL XIANAIN0,XIANAIN1,XIANAIN2,XIANAIN3,XIANAIN4,XIANAIN5,XIANAIN6,XIANAIN7 :  STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN 
u1 : ADD8 PORT MAP(A=>AIN0,B=>R0,C=>STMP1);
u2 : ADD8 PORT MAP(A=>AIN1,B=>R3,C=>STMP2);
u3 : ADD8 PORT MAP(A=>AIN0,B=>R3,C=>STMP3);
u4 : ADD8 PORT MAP(A=>AIN1,B=>R0,C=>STMP4);
u5 : ADD8 PORT MAP(A=>AIN2,B=>R1,C=>STMP5);
u6 : ADD8 PORT MAP(A=>AIN3,B=>R2,C=>STMP6);
u7 : ADD8 PORT MAP(A=>AIN2,B=>R2,C=>STMP7);
u8 : ADD8 PORT MAP(A=>AIN3,B=>R1,C=>STMP8);
u9 : ADD8 PORT MAP(A=>AIN4,B=>R1,C=>STMP9);
u10 : ADD8 PORT MAP(A=>AIN5,B=>R2,C=>STMP10);
u11 : ADD8 PORT MAP(A=>AIN4,B=>R2,C=>STMP11);
u12 : ADD8 PORT MAP(A=>AIN5,B=>R1,C=>STMP12);
u13 : ADD8 PORT MAP(A=>AIN6,B=>R0,C=>STMP13);
u14 : ADD8 PORT MAP(A=>AIN7,B=>R3,C=>STMP14);
u15 : ADD8 PORT MAP(A=>AIN6,B=>R3,C=>STMP15);
u16 : ADD8 PORT MAP(A=>AIN7,B=>R0,C=>STMP16);
U17 : MAXSTARTXT PORT MAP(XIN=>STMP1,YIN=>STMP2,KIN=>KIN,SOUTPUT=>NIN0);
U18 : MAXSTARTXT PORT MAP(XIN=>STMP3,YIN=>STMP4,KIN=>KIN,SOUTPUT=>NIN4);
U19 : MAXSTARTXT PORT MAP(XIN=>STMP5,YIN=>STMP6,KIN=>KIN,SOUTPUT=>NIN5);
U20 : MAXSTARTXT PORT MAP(XIN=>STMP7,YIN=>STMP8,KIN=>KIN,SOUTPUT=>NIN1);
U21 : MAXSTARTXT PORT MAP(XIN=>STMP9, YIN=>STMP10,KIN=>KIN,SOUTPUT=>NIN2);
U22 : MAXSTARTXT PORT MAP(XIN=>STMP11,YIN=>STMP12,KIN=>KIN,SOUTPUT=>NIN6);
U23 : MAXSTARTXT PORT MAP(XIN=>STMP13,YIN=>STMP14,KIN=>KIN,SOUTPUT=>NIN7);
U24 : MAXSTARTXT PORT MAP(XIN=>STMP15,YIN=>STMP16,KIN=>KIN,SOUTPUT=>NIN3);
U25 : COMPARE PORT MAP(AIN0=>NIN0,AIN1=>NIN1,AIN2=>NIN2,AIN3=>NIN3,AIN4=>NIN4,AIN5=>NIN5,AIN6=>NIN6,AIN7=>NIN7,AOUT=>LINSHI);
U26 : JIAN8 PORT MAP(A=>NIN0,B=>LINSHI,C=>XIANAIN0);
U27 : JIAN8 PORT MAP(A=>NIN1,B=>LINSHI,C=>XIANAIN1);
U28 : JIAN8 PORT MAP(A=>NIN2,B=>LINSHI,C=>XIANAIN2);
U29 : JIAN8 PORT MAP(A=>NIN3,B=>LINSHI,C=>XIANAIN3);
U30 : JIAN8 PORT MAP(A=>NIN4,B=>LINSHI,C=>XIANAIN4);
U31 : JIAN8 PORT MAP(A=>NIN5,B=>LINSHI,C=>XIANAIN5);
U32 : JIAN8 PORT MAP(A=>NIN6,B=>LINSHI,C=>XIANAIN6);
U33 : JIAN8 PORT MAP(A=>NIN7,B=>LINSHI,C=>XIANAIN7);

U34 :  CONTROL PORT MAP(CLK=>CLK,RESET=>RESET,SET=>SET,ADIN=>ADIN,WR=>LINEWR,ADOUT=>LINEADOUT);
U35 :  RAM_CHIP2 PORT MAP(INCLOCK=>CLK,ADDRESS=>LINEADOUT,WE=>LINEWR,DATA=>LINEDATA,Q=>LINEQ);
U36 :  FENXIN1 PORT MAP(DATA=>LINEQ,NAIN0=>LINEAIN0,NAIN1=>LINEAIN1,NAIN2=>LINEAIN2,NAIN3=>LINEAIN3,NAIN4=>LINEAIN4,NAIN5=>LINEAIN5,NAIN6=>LINEAIN6,NAIN7=>LINEAIN7);
U37 :  FENXIN2 PORT MAP(DATA=>LINEDATA,NAIN0=>XIANAIN0,NAIN1=>XIANAIN1,NAIN2=>XIANAIN2,NAIN3=>XIANAIN3,NAIN4=>XIANAIN4,NAIN5=>XIANAIN5,NAIN6=>XIANAIN6,NAIN7=>XIANAIN7);
KNAIN0<=LINEAIN0;
KNAIN1<=LINEAIN1;
KNAIN2<=LINEAIN2;
KNAIN3<=LINEAIN3;
KNAIN4<=LINEAIN4;
KNAIN5<=LINEAIN5;
KNAIN6<=LINEAIN6;
KNAIN7<=LINEAIN7;


 END;