compare4to2.vhd

使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY COMPARE4TO2 IS
   PORT(AIN0,AIN1,AIN2,AIN3 : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
          AOUT1, AOUT2 : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0)
   );
END;

ARCHITECTURE BEHV OF COMPARE4TO2 IS
BEGIN
PROCESS(AIN0,AIN1,AIN2,AIN3)

VARIABLE STMP1,STMP2 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN


 IF AIN0>AIN1 THEN STMP1:=AIN1; ELSE STMP1:=AIN0; END IF;
 IF AIN3>AIN2 THEN STMP2:=AIN2; ELSE STMP2:=AIN3; END IF;
  
 
         AOUT1<=STMP1;
         AOUT2<=STMP2; 
         
END PROCESS;
END;