add9.vhd

使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADD9 IS 
   PORT 
       ( A,B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                 C : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) );
END ADD9;
ARCHITECTURE HDLARCH OF ADD9 IS
COMPONENT ADD

PORT (AIN,BIN,CIN :IN STD_LOGIC;
          COUNT,SUM  : OUT STD_LOGIC);
END COMPONENT;

SIGNAL STMP : STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN 
STMP(0)<='0';   C(8)<=STMP(8);

GENSUB : FOR I IN 0 TO 7 GENERATE
U1 : ADD PORT MAP(AIN=>A(I),BIN=>B(I),CIN =>STMP(I),COUNT=>STMP(I+1),SUM=>C(I));

END GENERATE;
END;