suber.vhd

使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SUBER IS
PORT (X,Y,SUB_IN :IN STD_LOGIC;
      DIFFR,SUB_OUT : OUT STD_LOGIC);
END ENTITY;
ARCHITECTURE SCHARCH OF SUBER IS
COMPONENT H_SUBER
PORT (X,Y :IN STD_LOGIC;
      DIFF,S_OUT : OUT STD_LOGIC);
END COMPONENT;
SIGNAL T0,T1,T2: STD_LOGIC;
BEGIN 
U1: H_SUBER PORT MAP(X=>X,Y=>Y,DIFF=>T0,S_OUT=>T1);
U2: H_SUBER PORT MAP(X=>T0,Y=>SUB_IN,DIFF=>DIFFR,S_OUT=>T2);
SUB_OUT <=T1 OR T2;
END;