_primary.vhd

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity s_2_p is
    port(
        paral_data      : out    vl_logic_vector(7 downto 0);
        cnt             : in     vl_logic_vector(2 downto 0);
        sda             : in     vl_logic;
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        clk1            : in     vl_logic;
        flag            : out    vl_logic
    );
end s_2_p;