_primary.vhd

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity control is
    port(
        clk1            : out    vl_logic;
        cnt_for_mux     : out    vl_logic_vector(4 downto 0);
        cnt             : out    vl_logic_vector(2 downto 0);
        clk_488         : in     vl_logic;
        rst             : in     vl_logic;
        frame_clk       : in     vl_logic
    );
end control;