_primary.vhd

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity p_2_s is
    port(
        seria_out       : out    vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        cnt             : in     vl_logic_vector(2 downto 0);
        data_in         : in     vl_logic_vector(7 downto 0)
    );
end p_2_s;