_primary.vhd

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· VHDL 代码 · 共 45 行

library verilog;
use verilog.vl_types.all;
entity demux is
    port(
        rst             : in     vl_logic;
        clk             : in     vl_logic;
        clk1            : in     vl_logic;
        flag            : in     vl_logic;
        cnt             : in     vl_logic_vector(4 downto 0);
        data_in         : in     vl_logic_vector(7 downto 0);
        data_out0       : out    vl_logic_vector(7 downto 0);
        data_out1       : out    vl_logic_vector(7 downto 0);
        data_out2       : out    vl_logic_vector(7 downto 0);
        data_out3       : out    vl_logic_vector(7 downto 0);
        data_out4       : out    vl_logic_vector(7 downto 0);
        data_out5       : out    vl_logic_vector(7 downto 0);
        data_out6       : out    vl_logic_vector(7 downto 0);
        data_out7       : out    vl_logic_vector(7 downto 0);
        data_out8       : out    vl_logic_vector(7 downto 0);
        data_out9       : out    vl_logic_vector(7 downto 0);
        data_out10      : out    vl_logic_vector(7 downto 0);
        data_out11      : out    vl_logic_vector(7 downto 0);
        data_out12      : out    vl_logic_vector(7 downto 0);
        data_out13      : out    vl_logic_vector(7 downto 0);
        data_out14      : out    vl_logic_vector(7 downto 0);
        data_out15      : out    vl_logic_vector(7 downto 0);
        data_out16      : out    vl_logic_vector(7 downto 0);
        data_out17      : out    vl_logic_vector(7 downto 0);
        data_out18      : out    vl_logic_vector(7 downto 0);
        data_out19      : out    vl_logic_vector(7 downto 0);
        data_out20      : out    vl_logic_vector(7 downto 0);
        data_out21      : out    vl_logic_vector(7 downto 0);
        data_out22      : out    vl_logic_vector(7 downto 0);
        data_out23      : out    vl_logic_vector(7 downto 0);
        data_out24      : out    vl_logic_vector(7 downto 0);
        data_out25      : out    vl_logic_vector(7 downto 0);
        data_out26      : out    vl_logic_vector(7 downto 0);
        data_out27      : out    vl_logic_vector(7 downto 0);
        data_out28      : out    vl_logic_vector(7 downto 0);
        data_out29      : out    vl_logic_vector(7 downto 0);
        data_out30      : out    vl_logic_vector(7 downto 0);
        data_out31      : out    vl_logic_vector(7 downto 0)
    );
end demux;