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V 的代码
led.v
module Led(
Led_En_n,
Led,
Buzz,
Sev_Seg_Led_Sel_n
);
output Led_En_n; //定义输出口
output [7:0]Led; //定义输出口
output Buzz;
output [3:0] Sev_Seg_Led_Sel_n;
assign
basegate.v
module BaseGate(
Sw_n,
Led_En_n,
Led,
Buzz,
Sev_Seg_Led_Sel_n
);
input [3:0] Sw_n;
output Led_En_n;
output [7:0] Led;
output Buzz;
output [3:0] Sev
keyled.v
module KeyLed(
Sw_n,
Led_En_n,
Led,
Buzz,
Sev_Seg_Led_Sel_n
);
input [3:0] Sw_n;
output Led_En_n;
output [7:0] Led;
output Buzz;
output [3:0] Sev_Seg_Led_Sel_n;
timer.v
`include "Timer_Cout.v"
`include "Timer_Disp.v"
module Timer(
Clk,
Sw_n,
Sev_Seg_Led_Sel_n,
Sev_Seg_Led_Data_n,
Led_En_n
);
input Clk;
inpu
freque.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:02:31 08/06/2007
// Design Name:
// Modul
counter.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:56:05 04/29/2009
// Design Name:
// Modul
aaa.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
mac.v
module mac(input clk,
input reset,
input dv_enable,
input [7:0] rd_data_cha,
input [7:0] rd_data_chb,
input [7:0] rd_data_chc,
input [7:0] rd_data_chd,
input
mac.v
module mac(input clk,
input reset,
input dv_enable,
input [7:0] rd_data_cha,
input [7:0] rd_data_chb,
input [7:0] rd_data_chc,
input [7:0] rd_data_chd,
input
mac.v
module mac(input clk,
input reset,
input dv_enable,
input [7:0] rd_data_cha,
input [7:0] rd_data_chb,
input [7:0] rd_data_chc,
input [7:0] rd_data_chd,
input