aaa.v

本实例是学习fpga的入门程序 希望大家喜欢

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// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file aaa.v when simulating
// the core, aaa. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module aaa(
	A,
	B,
	C_IN,
	Q,
	CLK);


input [15 : 0] A;
input [15 : 0] B;
input C_IN;
output [15 : 0] Q;
input CLK;

// synthesis translate_off

      C_ADDSUB_V7_0 #(
		.C_ADD_MODE(0),
		.C_AINIT_VAL("0000"),
		.C_A_TYPE(1),
		.C_A_WIDTH(16),
		.C_BYPASS_ENABLE(0),
		.C_BYPASS_LOW(0),
		.C_B_CONSTANT(0),
		.C_B_TYPE(1),
		.C_B_VALUE("0"),
		.C_B_WIDTH(16),
		.C_ENABLE_RLOCS(1),
		.C_HAS_ACLR(0),
		.C_HAS_ADD(0),
		.C_HAS_AINIT(0),
		.C_HAS_ASET(0),
		.C_HAS_A_SIGNED(0),
		.C_HAS_BYPASS(0),
		.C_HAS_BYPASS_WITH_CIN(0),
		.C_HAS_B_IN(0),
		.C_HAS_B_OUT(0),
		.C_HAS_B_SIGNED(0),
		.C_HAS_CE(0),
		.C_HAS_C_IN(1),
		.C_HAS_C_OUT(0),
		.C_HAS_OVFL(0),
		.C_HAS_Q(1),
		.C_HAS_Q_B_OUT(0),
		.C_HAS_Q_C_OUT(0),
		.C_HAS_Q_OVFL(0),
		.C_HAS_S(0),
		.C_HAS_SCLR(0),
		.C_HAS_SINIT(0),
		.C_HAS_SSET(0),
		.C_HIGH_BIT(15),
		.C_LATENCY(1),
		.C_LOW_BIT(0),
		.C_OUT_WIDTH(16),
		.C_PIPE_STAGES(1),
		.C_SINIT_VAL("0"),
		.C_SYNC_ENABLE(0),
		.C_SYNC_PRIORITY(1))
	inst (
		.A(A),
		.B(B),
		.C_IN(C_IN),
		.Q(Q),
		.CLK(CLK),
		.ACLR(),
		.ADD(),
		.AINIT(),
		.ASET(),
		.A_SIGNED(),
		.B_OUT(),
		.B_SIGNED(),
		.C_OUT(),
		.B_IN(),
		.BYPASS(),
		.CE(),
		.OVFL(),
		.Q_C_OUT(),
		.Q_B_OUT(),
		.Q_OVFL(),
		.S(),
		.SCLR(),
		.SINIT(),
		.SSET());


// synthesis translate_on

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of aaa is "black_box"

endmodule