freque.v

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:02:31 08/06/2007 
// Design Name: 
// Module Name:    freque 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module freque(CLK, RST_N, FREQUECEIN, HC_SI, HC_CP);
    input CLK;
    input RST_N;
    input FREQUECEIN;
    output HC_SI;
    output HC_CP;
	
	reg periode0,periode1;
	wire periode_pos ;
	wire CLK0_OUT ;
	wire CLKFX_OUT ;
	wire CLK2X_OUT ;
	always @ (posedge CLK2X_OUT or negedge RST_N)
	begin
	if(!RST_N)
		begin
			periode0 <= 0;
			periode1 <= 0;
		end
	else 
		begin
		periode0 <= FREQUECEIN ;
		periode1 <= periode0 ;
		end
	end
	
	assign periode_pos = periode0 && (!periode1) ;
	
	reg [23:0] fre_count;
	reg [23:0] fre_temp ;
	always @ (posedge CLK2X_OUT or negedge RST_N)
		begin
			if(!RST_N)
				begin
					fre_count <= 0 ;
					fre_temp <= 0 ;
				end
			else if (periode_pos)
					begin
					fre_temp <= 0 ;
					if(fre_temp > 10)
					fre_count <= fre_temp ;
					end
			else 
				fre_temp <= fre_temp + 1 ;
		end
	
	wire [ 23 : 0 ] data_value ;
	reg [ 21 : 0 ] display_cnt ;
//	reg [ 11 : 0 ] display_cnt ;
//	wire display_clk ;
		always @ (posedge CLK0_OUT or negedge RST_N)
		begin
			if(!RST_N)
				display_cnt <= 0 ;
			else 
				display_cnt <= display_cnt + 1;
		end	
	assign data_value = (display_cnt == 22'h3fffff) ?  fre_count : data_value ;
hc_led hc_ledtop(
    .clk(CLK0_OUT), 
    .rst_n(RST_N), 
    .led(data_value[7:4]), 
   // .dot(data_value[7:4]), 
	 .dot(0'b0000), 
    .data_value(data_value[23 : 8]), 
    .hc_cp(HC_CP), 
    .hc_si(HC_SI)
    );

clk200hz clk200hztop (
    .CLKIN_IN(CLK), 
    .RST_IN(!RST_N), 
    .CLKFX_OUT(CLKFX_OUT), 
    .CLKIN_IBUFG_OUT(), 
    .CLK0_OUT(CLK0_OUT), 
    .CLK2X_OUT(CLK2X_OUT), 
    .LOCKED_OUT()
    );

endmodule