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V 的代码
mutli.v
module mutli (a,b,q);
input[3:0] a,b;
output[4:0] q;
assign q=a+b;
endmodule
cfq.v
module cfq (data,clk,q);//上生沿触发器
input data,clk;
output q;
reg q;
always @(posedge clk)
q=data;
endmodule
dispselect.v
module dispselect(clk,disp_select,Q);
output [5:0] Q;
output [2:0] disp_select;
input clk;
reg [5:0] Q;
reg [2:0] disp_select;
always @(posedge clk)
begin
if(disp_select < 3'b101)
d
counter.v
module counter(EN,CLR,F_IN,F_OUT,Q0,Q1,Q2,Q3,Q4,Q5);
output [3:0] Q5,Q4,Q3,Q2,Q1,Q0;
output F_OUT;//超过量程提示用户注意
input EN;//主要功能是门控模块根据外界量程的选择来控制计数器的工作情况
input CLR;
input F_IN;
reg [3:0] Q5
fdiv.v
module fdiv(clk,f1hz,f10hz,f100hz,f1khz);
output f1hz,f10hz,f100hz,f1khz;
input clk;
reg f1hz,f10hz,f100hz,f1khz;
integer cnt1=0,cnt2=0,cnt3=0,cnt4=0;
always @(posedge clk)
begin
//if(c
main.v
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
dispdecoder.v
module dispdecoder(
data_in,//BCD码字输入信号
disp_select,
dp_s1hz,dp_s10hz,dp_s100hz,
Q5,Q4,Q3,Q2,Q1,Q0,
counter_out,//计数溢出信号
data_out,
dp);//小数点控制信号
output [6:
fdiv.v
module fdiv(
Reset,
Clock_8MHz,
F_65536Hz,
F_1Hz
);
output F_65536Hz;
output F_1Hz;
input Reset;
input Clock_8MHz;
reg [22:0] CNT;
//全局时钟经过100分频后得到65536Hz时钟信号
always @
main.v
// Copyright (C) 1991-2004 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any
alarmclock.v
module alarmclock(
clk_200hz,
EN,
SW1,SW2,
hour1,hour0,
minute1,minute0,
second1,second0,
alarm,
alarmclock_disp_select); //闹钟设置中的位选