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V 的代码
tellpw.v
module tellpw(DIN,DATA,cfm,ok,n,lock,mis);
input[23:0] DIN,DATA;
input cfm;
output ok,lock,mis;
output[1:0] n;
reg ok,lock,mis;
reg[1:0] n;
always @(posedge cfm)
begin
if(DIN==DATA)
be
keyvalue.v
module KEYVALUE(clk,d,dout);
input clk;
input[7:0] d;
output[3:0] dout;
reg[3:0] dout;
always @(posedge clk)
begin
case(d)
8'b1000_1000: dout=4'b0000;
8'b1000_0100: dout=4'b0001;
8'
control.v
module control(en,D,DATA,cfm,shift);
input en;
input[3:0] D;
output cfm,shift;
output[23:0] DATA;
reg[23:0] DATA;
reg cfm,shift;
integer i;
always @(negedge en)
begin
cfm=0;
if(D[3:0]
tellpw.v
module tellpw(DIN,DATA,cfm,ok,n,lock);
input[23:0] DIN,DATA;
input cfm;
output ok,lock;
output[1:0] n;
reg ok,lock;
reg[1:0] n;
always @(posedge cfm)
begin
if(DIN==DATA)
begin
n=0;
decide.v
module decide(y,a);
output y;
input[6:0] a;
wire[2:0] x;
reg y;
assign x=a[0]+a[1]+a[2]+a[3]+a[4]+a[5]+a[6];
always
begin
if(x[2]==1)
y=1;
else
y=0;
end
endmodule
control.v
module control(en,D,DATA,cfm);
input en;
input[3:0] D;
output cfm;
output[23:0] DATA;
reg[23:0] DATA;
reg cfm;
integer i=7;
always @(negedge en)
begin
cfm=0;
if(D[3:0]
keyvalue.v
module KEYVALUE(clk,d,dout);
input clk;
input[7:0] d;
output[3:0] dout;
reg[3:0] dout;
always @(posedge clk)
begin
case(d)
8'b1000_1000: dout=4'b0000;
8'b1000_0100: dout=4'b0001;
8'
control.v
module control(en,D,DATA,cfm,shift);
input en;
input[3:0] D;
output cfm,shift;
output[23:0] DATA;
reg[23:0] DATA;
reg cfm,shift;
integer i;
always @(negedge en)
begin
cfm=0;
if(D[3:0]
keyvalue.v
module KEYVALUE(clk,d,dout);
input clk;
input[7:0] d;
output[3:0] dout;
reg[3:0] dout;
always @(posedge clk)
begin
case(d)
8'b1000_1000: dout=4'b0000;
8'b1000_0100: dout=4'b0001;
8'
mutli.v
module mutli (a,b,q);
input[3:0] a,b;
output[4:0] q;
assign q=a+b;
endmodule