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counter.v
module counter ( clock,
reset,
data_bus_in,
cnt_out
);
input clock, reset;
input [7:0] data_bu
decode.v
module decode (clock, reset, data_bus_in, addr_bus, data_bus_out);
input clock, reset;
input [7:0] data_bus_in;
input [7:0] addr_bus;
output [7:0] data_bus_out;
reg [7:0] data_bu
bibus.v
module bibus (clk, rst, sel, data_bus, addr);
input clk, rst, sel;
input [7:0] addr;
inout [7:0] data_bus;
wire [7:0] data_in, data_out;
assign data_in = data_bus;
assign data_bus = (sel
decode.v
module decode (clock, reset, data_bus_in, addr_bus, data_bus_out);
input clock, reset;
input [7:0] data_bus_in;
input [7:0] addr_bus;
output [7:0] data_bus_out;
reg [7:0] data_bu
fulladderx.v
module oneadder(A, B, C1, S, C2);
input A, B, C1;
output S, C2;
assign S = A ^ B ^ C1;
assign C2 = (A & B) | (A & C1) | (B & C1);
endmodule
module FullAdder ( A, B, S, c_1,cs);
input [3:0]