fulladderx.v

全加器verilog程序

module  oneadder(A, B, C1, S, C2);
input	 A, B, C1;
output	  S, C2;

assign   S  = A ^ B ^ C1;
assign  C2 = (A & B) | (A & C1) | (B & C1);

endmodule 

module FullAdder	( A, B, S, c_1,cs);
input [3:0] A, B;
input c_1;
output 	[3:0] S;
output cs;
wire [2:0] CY;
    oneadder	U0 (A[0], B[0], c_1, S[0], CY[0]);
  	oneadder	U1 (A[1], B[1], CY[0], S[1], CY[1]);
 	oneadder	U2 (A[2], B[2], CY[1], S[2], CY[2]);
  	oneadder	U3 (A[3], B[3], CY[2], S[3], cs);
endmodule