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V 的代码
stm.v
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Verilog Design & Verification
// EDA Pioneer
// - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`timesca
spram.v
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: SPRAM.v
//
fulladd.v
module HalfAdd (X, Y, SUM, C_out);//半加器模块
input X;
input Y;
output SUM;
output C_out;
assign SUM = X ^ Y ;
assign C_out = X & Y ;
endmodule
module FullAdd (X, Y, C_in, SUM, C_out);//全加器模块
i
mux.v
module mux (en, a, b, c, d, mux_out);
input [1:0] en;
input a, b, c, d;
output mux_out;
reg mux_out;
always @ (en or a or b or c or d)
case(en)
2'b00: mux_ou
mux.v
module mux (en, a, b, c, d, mux_out);
input [1:0] en;
input a, b, c, d;
output mux_out;
reg mux_out;
always @ (en or a or b or c or d)
case(en)
2'b00: mux_ou
hellovlog.v
//以下是编译指令，定义时间单位和时间精度
`timescale 1ns / 100ps
//以下是module名称, 端口列表
module HelloVlog ( Clock, Reset_n, A_in, B_in, Sel_in, A_xor_out, B_xor_out );
//以下是输入和输出端口声明
input Clock;
input Reset_n;
i
fhtpart.v
module fhtpart(Clk,Reset,FhtStarOne,FhtStarTwo,FhtStarThree,FhtStarFour,
I0,I1,I2,I3,I4,I5,I6,I7,I8,
I9,I10,I11,I12,I13,I14,I15,
Out0,Out1,Out2,Out3,Out4,Out5,Out6,
fhtpart.v
module fhtpart(Clk,Reset,FhtStarOne,FhtStarTwo,FhtStarThree,FhtStarFour,
I0,I1,I2,I3,I4,I5,I6,I7,I8,
I9,I10,I11,I12,I13,I14,I15,
Out0,Out1,Out2,Out3,Out4,Out5,Out6,
fulladd.v
module HalfAdd (X, Y, SUM, C_out);//半加器模块
input X;
input Y;
output SUM;
output C_out;
//assign SUM = X ^ Y ;
//assign C_out = X & Y ;
xor u_xor (SUM, X, Y); //门级原语实例
and u_and (C_out, X, Y); /
single_if.v
module single_if(a, b, c, d, sel0, sel1, sel2, sel3, z);
input a, b, c, d;
input sel0, sel1, sel2, sel3;
output z;
reg z;
always @(a or b or c or d or sel0 or sel1 or sel2 or sel3)
begin