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lwbdecode.v
/////////////////////////////////////////////////////////////////////
//// ////
//// LWB rev 1.2 -- Memory Address Decode
and2.v
/* AND2 */
module AND2 ( A, B, OUT );
input A, B;
output OUT;
and U1 ( OUT, A, B );
endmodule
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
top.v
module top (rst, CS_, OE_, WR_, Addr, data_bus);
input rst;
input CS_, OE_, WR_;
input [7:0] Addr;
inout [7:0] data_bus;
wire [7:0] data_in;
wire [7:0] data_out;
wire my_
decode.v
// decode circuit, combination logic
module decode (CS_, OE_, WR_, Addr, my_wr, my_rd, CS_reg1, CS_reg2, CS_reg3);
input CS_, OE_, WR_;
input [7:0] Addr;
output my_wr, my_rd;
top.v
module top (rst, CS_, OE_, WR_, Addr, data_bus);
input rst;
input CS_, OE_, WR_;
input [7:0] Addr;
inout [7:0] data_bus;
wire [7:0] data_in;
wire [7:0] data_out;
wire my_
decode.v
// decode circuit, combination logic
module decode (CS_, WR_, Addr, my_wr, my_rd, CS_reg1, CS_reg2, CS_reg3);
input CS_, WR_;
input [7:0] Addr;
output my_wr, my_rd;
output