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V 的代码
disp.v
//
// decoder for 7 led display
//
module disp (in, out);
input [7:0] in;
output [13:0] out;
reg [13:0] out;
always @(in)
begin
case (in[7:4])
4'h0: out[13:7] = 7'b1110111;
rdfifo.v
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: rdfifo.v
// Megafuncti
datagene.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company :
// Engineer :
// Create Date :
// Design Name :
// Module Name : datagene
wrfifo.v
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: wrfifo.v
// Megafuncti
ddsqam.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
lcd.v
module lcd(sram_data,in_out_data,clk_in_data,clkin,OE,CE,WE,LB,UB,ADDER,DE,CLKOUT,HSYNC,YSYNC,PON,HL,JGND,DATA,led1,led2);
inout [15:0] sram_data;
input [15:0] in_out_data;
input clkin,clk_in_data;
testtry.v
module test(clk,rst,
data,addr,ba,
sdclk,cke,
cs_n,ras_n,cas_n,we_n,dqm,
flash_ce,flash_oe,flash_rw,
sram_ce,sram_oe,sram_we,sram_be,
data_out,led);
input
testtry.v
module test(clk,rst,
data,addr,ba,
sdclk,cke,
cs_n,ras_n,cas_n,we_n,dqm,
flash_ce,flash_oe,flash_rw,
sram_ce,sram_oe,sram_we,sram_be,
data_out,led);
input
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi