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taskwait.v
module TaskWait;
//reg NoClock;
reg ClockQ;
task GenerateWaveform;
begin
ClockQ=1;
#2 ClockQ=0;
#2 ClockQ=1;
#2 ClockQ=0;
end
endtask
initial
GenerateWaveform;
end
sdram.v
`include "inc.h"
//
// SDRAM Controller.
//
// Hierarchy:
//
// SDRAM.V Wrapper.
// HOSTCONT.V Controls the interfacing between the micro and the SDRAM
// SDRAMCNT.V This is th
micro.v
`include "tst_inc.h"
`include "inc.h"
module micro(
// system connections
mp_clk,
sys_rst_l,
// Connections to the HOSTCONT.V
sdramcnt.v
`include "inc.h"
//
// SDRAMCNT.v
//
// SDRAM controller.
// This module can control Synchronous DRAMS such as
// Samsumg's KM416S1020/KM416S1120 1MB X 16
// NEC's uPD451616
hostcont.v
`include "inc.h"
/*
** HOSTCONT.v
**
** This module is the host controller whic sits between the host
** (usually a micro) and the sdramcnt.v
**
**
**
**
*/
module hostcont (
tfsm.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
mfsm.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
acounter.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
errloc.v
//-------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE
md.v
/******************************************************************************
*
* File Name: md.v
* Version: 1.1
* Date: January 22, 2000
* Model: Manchester Decoder
*
*