lcd.v

stm32数码相框

module lcd(sram_data,in_out_data,clk_in_data,clkin,OE,CE,WE,LB,UB,ADDER,DE,CLKOUT,HSYNC,YSYNC,PON,HL,JGND,DATA,led1,led2);
inout [15:0] sram_data;
input [15:0] in_out_data;
input clkin,clk_in_data;
output DE,CLKOUT,HSYNC,YSYNC,PON,HL,led1,led2,OE,CE,WE,LB,UB,ADDER;
output [15:0]DATA;
output [7:0]JGND;
reg DE,CLKOUT,HSYNC,YSYNC,DEX,PON,TONG,HL,led1,led2,OE,CE,WE,LB,UB,read_need,read,in_rw,rw_o,tt,te,delay;
reg [15:0] DATA;
reg [17:0] ADDER;
reg [17:0] ADDER_TFT;
reg [17:0] ADDER_CON;
reg [5:0] temp;
reg [9:0] tmp;
reg [9:0] temp1;
reg [10:0] temp3;
reg [10:0] temp4;
reg [9:0] temp2;
reg [7:0] JGND;
reg [27:0] jishu1;
reg [27:0] jishu2;
reg [4:0] state;
reg [15:0] rw_data;
reg [15:0] rd_data;
reg [1:0] rw;
reg [4:0] shi;
initial
begin

	DE=1'b0;
	CLKOUT=1'b0;
	HSYNC=1'b0;
	YSYNC=1'b0;
	temp=0;
	tmp=0;
	te=1'b1;
	JGND=8'hff;
	HL=1'b1;
	temp1=0;
	temp2=0;
	temp3=0;
	temp4=0;
	delay=0;
	PON=1'b0;
	TONG=1'b0;
	DATA=16'hffff;
	OE=1'b1;
	CE=1'b1;
	WE=1'b1;
	read_need=1'b0;
	in_rw=1'b1;
	rw=1'b1;
	rd_data=16'hf800;
	ADDER_TFT=18'b00_0000_0000_0000_0000;
	ADDER_CON=18'b00_0000_0000_0000_0000;
	shi=4'b0000;
end

assign sram_data=(rw_o==te)? rw_data:16'hzzzz;

always@(posedge clkin)
if(delay)
begin
	if(temp==6'd14)
	begin	
		CLKOUT=~CLKOUT;
		temp=0;
	end
	else	
		temp=temp+1'b1;
end




always@(posedge clkin)
begin
	if(jishu1==27'd50000000)
	begin	
		led1=~led1;
		jishu1<=0;
	end
	else
	
		jishu1<=jishu1+1'b1;

end

always@(posedge clkin)
begin
	if(jishu2==27'd10000000)
	begin	
		//led2=~led2;
		delay=1;
		jishu2=0;
	end
	else
	
		jishu2<=jishu2+1'b1;

end


always@(posedge clkin)
begin
	if(delay)
		begin
	if(state==6'd14)
	begin	
		state=0;
	end
	else	
		state=state+1'b1;
end
end

always@(posedge clkin)
if(delay)		
begin
	case (state)
               1:begin
                    if(read_need==1)
                    begin
						led2=0;
						ADDER<=ADDER_TFT;
						read=1;
					end
                 end
                2:begin
                    if(read==1)
                    begin
						CE<=0;
					end
				  end 
				3:begin
                    if(read==1)
                    begin
						OE<=1'b0;
						WE<=1'b1;
						UB<=1'b0;
						LB<=1'b0;
						
					end
				  end
				  
			
				4:begin
                    if(read==1)
						begin
							ADDER_TFT<=ADDER_TFT+1;
							OE<=1'b1;
							CE<=1'b1;

							
							read<=1'b0;
							
						end					
					end	
					
				5:begin
                    
							DATA<=sram_data;				
					end
					
				6:begin
                    
						begin
							ADDER<=18'hzzzzz;
							UB<=1'b1;
							LB<=1'b1;
						end					
					end
					
				7:begin
                    if(in_rw==1)
						begin
							ADDER<=ADDER_CON;
							rw<=1'b1;
							led2=1;
						end					
					end
				8:begin
                    if(rw==1)
						begin
							CE<=1'b0;
							WE<=1'b0;
							UB<=1'b0;
							LB<=1'b0;
							led2=1;
							rw_o<=1'b1;
						end					
					end
				
				10:begin
                    if(rw==1)
						begin
							CE<=1'b1;
							WE<=1'b1;
							UB<=1'b1;
							LB<=1'b1;
						end					
					end

				11:begin
                    if(rw==1)
						begin
							
							ADDER_CON<=ADDER_CON+1'b1;
							ADDER<=18'hzzzzz;
							rw<=1'b0;
							rw_o<=1'b0;
							if(shi==4)in_rw<=1'b0;
						end					
					end
					
								
				
				12:begin
                    
							if(temp2==9'd286)
								begin
									ADDER_TFT<=0;
									ADDER_CON<=0;
									
								end
								
					end			
              default:temp3=temp3+1'b1;
           endcase
end

always@(posedge clkin)
 begin
							if(shi==1)rw_data<=16'hf800;
							else if(shi==2)rw_data<=16'h001f;
							else if(shi==3)rw_data<=16'h07e0;
							
end



always@(posedge CLKOUT)
if(delay)
begin
	temp1=temp1+1'b1;
	if(temp1==6'd41)
	begin
		HSYNC=1'b1;
		
	end
		
	else if(DEX&temp1==6'd45)
	begin
		DE=1'b1;
		TONG=1'b1;
		PON=1'b1;
		JGND=8'hff;
		read_need=1'b1;
	end


else if(temp1==10'd285)
JGND=8'h00;
		
	else if(temp1==10'd533)
	begin	
		HSYNC=1'b0;
		DE=1'b0;
		TONG=1'b0;
		temp1=0;
		read_need=1'b0;
		end
end

always@(posedge HSYNC)
if(delay)
	begin
	temp2=temp2+1'b1;
	
	if(temp2==4'd11)
		begin
		YSYNC=1'b1;
		end
	else if(temp2==4'd13)
		begin
			DEX=1'b1;
		end
	else if(temp2==9'd105)
		shi=1;
	else if(temp2==9'd185)
		shi=2;
	else if(temp2==9'd245)
		shi=3;
	else if(temp2==9'd286)
		begin
		DEX=1'b0;
		shi=4;
		end	
	
		
		
	if(temp2==9'd289)
	begin
		YSYNC=1'b0;
		temp2=0;

	end
end
endmodule