📄 testtry.v
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module test(clk,rst,
data,addr,ba,
sdclk,cke,
cs_n,ras_n,cas_n,we_n,dqm,
flash_ce,flash_oe,flash_rw,
sram_ce,sram_oe,sram_we,sram_be,
data_out,led);
input clk,rst ;
inout [15:0 ] data ;
output [11:0 ] addr ;
output [1 :0 ] ba ;
output sdclk,cke ;
output cs_n,ras_n,cas_n,we_n ;
output [1 :0 ] dqm ;
output flash_ce,flash_oe,flash_rw ;
output sram_ce,sram_oe,sram_we ;
output [1 :0 ] sram_be ;
output [15:0 ] data_out ;
output led ;
wire flash_ce = 1 ;
wire flash_oe = 1 ;
wire flash_rw = 1 ;
wire sram_ce = 1 ;
wire sram_oe = 1 ;
wire sram_we = 1 ;
wire [1 :0 ] sram_be = 2'b11 ;
reg [15 : 0] dq; // SDRAM I/O
reg [11 : 0] addr; // SDRAM Address
reg [1 : 0] ba; // Bank Address
wire sdclk; // Clock
reg cke; // Synchronous Clock Enable
reg cs_n; // CS#
reg ras_n; // RAS#
reg cas_n; // CAS#
reg we_n; // WE#
reg [1 : 0] dqm; // I/O Mask
reg led ;
reg [15 :0 ] data_out ;
reg [5 :0 ] state_cnt ;
wire [15 : 0] data = dq;
assign sdclk = clk ;
always @ ( posedge clk or negedge rst )
if( !rst )
data_out <= 16'b0 ;
else
data_out <= dq ;
parameter hi_z = 16'bz; // Hi-Z
parameter half_clk = 5;
parameter full_clk = 10;
parameter testdata0 = 100 ;
parameter testdata1 = 111 ;
task active;
input bank;
input [11 : 0] row;
input [15 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 1;
dqm = 0;
ba = bank;
addr = row;
dq = dq_in;
end
endtask
task auto_refresh;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 0;
we_n = 1;
dqm = 0;
ba = 0;
addr = 0;
dq = hi_z;
end
endtask
task burst_term;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 1;
we_n = 0;
dqm = 0;
ba = 0;
addr = 0;
dq = hi_z;
end
endtask
task load_mode_reg;
input [12 : 0] op_code;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 0;
we_n = 0;
dqm = 0;
ba = op_code [12 :11];
addr = op_code [10 : 0];
dq = hi_z;
end
endtask
task nop;
input [1 : 0] dqm_in;
input [15 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 1;
we_n = 1;
dqm = dqm_in;
ba = 0;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_0;
input [1 : 0] dqm_in;
input [15 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 0;
addr = 0;
dq = dq_in;
end
endtask
task precharge_bank_1;
input [1 : 0] dqm_in;
input [15 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 1;
addr = 0;
dq = dq_in;
end
endtask
task precharge_all_bank;
input [1 : 0] dqm_in;
input [15 : 0] dq_in;
begin
cke = 1;
cs_n = 0;
ras_n = 0;
cas_n = 1;
we_n = 0;
dqm = dqm_in;
ba = 0;
addr = 1024; // A10 = 1
dq = dq_in;
end
endtask
task read;
input bank;
input [7 : 0] column;
input [15 : 0] dq_in;
input [1 : 0] dqm_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 0;
we_n = 1;
dqm = dqm_in;
ba = bank;
addr = column;
dq = dq_in;
end
endtask
task write;
input bank;
input [7 : 0] column;
input [15 : 0] dq_in;
input [1 : 0] dqm_in;
begin
cke = 1;
cs_n = 0;
ras_n = 1;
cas_n = 0;
we_n = 0;
dqm = dqm_in;
ba = bank;
addr = column;
dq = dq_in;
end
endtask
always @ ( posedge clk or negedge rst )
if( !rst )
begin
state_cnt <= 6'b000_000 ;
end
else
begin
if( 6'b111_000 <= state_cnt )
state_cnt <= 6'b000_000 ;
else
state_cnt <= state_cnt + 6'b000_001 ;
end
always @ ( posedge clk or negedge rst )
if( !rst )
begin
cke = 0;
cs_n = 1;
ras_n = 1;
cas_n = 1;
we_n = 1;
dqm = 3;
ba = 0;
addr = 0;
dq = hi_z;
led = 0 ;
end
else
begin
case( state_cnt )
'd0 : nop (0, hi_z); //0-8 Nop
'd9 : precharge_all_bank(0, hi_z); //9 Precharge ALL Bank
'd10: nop (0, hi_z); //10-11 Nop
'd12: auto_refresh; //12 Auto Refresh
'd13: nop (0, hi_z); //13-20 Nop
'd21: auto_refresh; //21 Auto Refresh
'd22: nop (0, hi_z); //22-29 Nop
'd30: load_mode_reg (547); //30 Load Mode: Lat = 2, BL = 8, Seq
'd31: nop (0, hi_z); //31 Nop
'd32: active (0, 0, hi_z); //32 Active: Bank = 0, Row = 0
'd33: nop (0, hi_z); //33-34 Nop
'd35: write (0, 200, testdata0, 0); //35 Write : Bank = 0, Col = 0, Dqm = 0
'd36: nop (0, hi_z); //36 Nop
'd37: nop (0, hi_z); //37 Nop
'd38: nop (0, hi_z); //38-40 Nop
'd41: active (0, 0, hi_z); //41 Active: Bank = 0, Row = 0
'd42: nop (0, hi_z); //42-43 Nop
'd44: write (0, 201, testdata1, 0); //44 Write : Bank = 0, Col = 0, Dqm = 0
'd45: nop (0, hi_z); //45 Nop
'd46: nop (0, hi_z); //46 Nop
'd47: nop (0, hi_z); //47-49 Nop
'd50: active (0, 0, hi_z); //50 Active: Bank = 0, Row = 0
'd51: nop (0, hi_z); //51-52 Nop
'd53: read (0, 200, hi_z, 0); //53 Nop
'd54: nop (0, hi_z); //54 Nop
'd55: nop (0, hi_z); //55 Nop
'd56: nop (0, hi_z); //56 Nop
'd56: begin
if( testdata0==dq )
led=0 ;
else
led=1 ;
end
'd0 : begin
if( testdata0==dq )
led=0 ;
else
led=1 ;
end
endcase
end
endmodule
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