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V 的代码
v_comments.v
`define ThirtyTwo 32
module v_comments ( a, // Pragma for a
b, // pragma for b
c,
d, d1, d2, d3 );
input a; // comment for a
v_gate.v
module buffer (
output Z,
input A);
buf u_buf(Z, A);
endmodule
module gate (
output Z,
input A);
buffer u_buf(Z, A);
endmodule
seven_v.v
module seven_v(d,s);
input[3:0] d;
output[0:6] s;
reg[0:6] s;
always
begin
case(d)
0: s=7'b1111110;
1: s=7'b0000110;
2: s=7'b1101101;
3: s=7'b1111001;
4: s=7'b0110011;
stmach_v.v
// C:\TEMP\CASE\WTUT_VER\STMACH_V.v
// Verilog created by Xilinx's StateCAD 7.1i
// Wed Feb 02 13:38:11 2005
// This Verilog code (for use with Synopsys) was generated using:
// binary enc
stmach_v.v
// C:\TEMP\CASE\WTUT_VER\STMACH_V.v
// Verilog created by Xilinx's StateCAD 7.1i
// Wed Feb 02 13:38:11 2005
// This Verilog code (for use with Synopsys) was generated using:
// binary enc
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
v_sync.v
//----------------------------------------------------------------------------
// VSYNC Generator - Sub-Level Module
//--------------------------------------------------------------------------