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V 的代码
v_sync.v
//----------------------------------------------------------------------------
// VSYNC Generator - Sub-Level Module
//--------------------------------------------------------------------------
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
stmach_v.v
// J:\ISE\WATCH_SC\STMACH_V.v
// Verilog created by Xilinx's StateCAD 5.1i
// Wed Dec 04 09:42:10 2002
// This Verilog code (for use with Xilinx XST) was generated using:
// one-hot state
quant_v.v
/**********************************************************************
** -----------------------------------------------------------------------------**
** quant.v
**
** Quantization
**
**
iquant_v.v
/**********************************************************************
** -----------------------------------------------------------------------------**
** iquant.v
**
** Quantization
**
**