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找到约 7,641 项符合
V 的代码
verilog.v
// generated by newgenasym Tue Nov 04 09:34:48 2008
module \74lvth125 (a1, a2, a3, a4, gnd, oe1_n, oe2_n, oe3_n, oe4_n, vcc, y1, y2, y3,
y4);
input a1;
input a2;
input a3;
verilog.v
// generated by newgenasym Tue Oct 21 18:34:25 2008
module lm317 (adj, in, out);
input adj;
input in;
input out;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Wed Oct 29 23:14:11 2008
module \74lvth244 (\1a1 , \1a2 , \1a3 , \1a4 , \1oe_n , \1y1 , \1y2 , \1y3 , \1y4 , \2a1 , \2a2 , \2a3 ,
\2a4 , \2oe_n , \2y1 , \2y2 , \
verilog.v
// generated by newgenasym Tue Nov 04 14:14:39 2008
module mpc8641d (agnd_srds1, agnd_srds2, asleep, avdd_core0, avdd_core1,
avdd_lb, avdd_plat, avdd_srds1, avdd_srds2, \ckstp_in* ,
verilog.v
// generated by newgenasym Fri Oct 24 14:14:46 2008
module dg419 (gnd, ina1, ina2, ind, out, van, vap, vd);
input gnd;
input ina1;
input ina2;
input ind;
input out;
input va
verilog.v
// generated by newgenasym Fri Oct 24 14:59:30 2008
module opampadj (m, n1, n2, out, p, vm, vp);
input m;
output n1;
input n2;
output out;
input p;
input vm;
input vp;
verilog.v
// generated by newgenasym Tue Oct 28 15:34:22 2008
module mt47j64m16 (a0, a1, a10, a11, a12, a2, a3, a4, a5, a6, a7, a8, a9, ba0, ba1,
ba2, \cas# , ck, \ck# , cke, \cs# , dq0, dq1, dq10, d
verilog.v
// generated by newgenasym Thu Oct 23 15:04:42 2008
module ic574 (c1, d0, d1, d2, d3, d4, d5, d6, d7, en, o0, o1, o2, o3, o4, o5, o6,
o7);
input c1;
input d0;
input d1;
inpu
verilog.v
// generated by newgenasym Thu Oct 30 14:40:37 2008
module lt3080 (in, out1, out2, set);
input in;
output out1;
output out2;
input set;
initial
begin
end
endm
verilog.v
// generated by newgenasym Wed Oct 29 11:37:46 2008
module dio (a, k);
inout a;
inout k;
initial
begin
end
endmodule