stmach_v.v

FPGA-CPLD_DesignTool(8-9-10)源代码

//  J:\ISE\WATCH_SC\STMACH_V.v
//  Verilog created by Xilinx's StateCAD 5.1i
//  Wed Dec 04 09:42:10 2002

//  This Verilog code (for use with Xilinx XST) was generated using: 
//  one-hot state assignment with boolean code format.
//  Minimization is disabled,  implied else is enabled, 
//  and outputs are speed optimized.

`timescale 1s/1s

module stmach_v(CLK,reset,strstop,clkout,rst);

	input CLK;
	input reset,strstop;
	output clkout,rst;
	reg clkout,next_clkout,rst,next_rst;
	reg CLEAR,next_CLEAR,counting,next_counting,start,next_start,stop,next_stop,
		stopped,next_stopped,zero,next_zero;

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) CLEAR = 1;
		else CLEAR = next_CLEAR;
	end

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) counting = 0;
		else counting = next_counting;
	end

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) start = 0;
		else start = next_start;
	end

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) stop = 0;
		else stop = next_stop;
	end

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) stopped = 0;
		else stopped = next_stopped;
	end

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) zero = 0;
		else zero = next_zero;
	end

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) clkout = 0;
		else clkout = next_clkout;
	end

	always @(posedge CLK or posedge reset)
	begin
		if ( reset ) rst = 1;
		else rst = next_rst;
	end

	always @ (CLEAR or counting or start or stop or stopped or strstop or zero)
	begin

		if ( ( CLEAR  & ( ~( ( 1'h1 ) ) ) )) next_CLEAR=1;
		else next_CLEAR=0;

		if ( ( counting  & ( ~( ( strstop  ) | ( ~strstop  ) ) ) ) | ( counting  & 
			( ~strstop  ) ) | ( start  & ( ~strstop  ) )) next_counting=1;
		else next_counting=0;

		if ( ( start  & ( ~( ( ~strstop  ) | ( strstop  ) ) ) ) | ( start  & ( 
			strstop  ) ) | ( stopped  & ( strstop  ) ) | ( zero  & ( strstop  ) )) 
			next_start=1;
		else next_start=0;

		if ( ( counting  & ( strstop  ) ) | ( stop  & ( ~( ( ~strstop  ) | ( 
			strstop  ) ) ) ) | ( stop  & ( strstop  ) )) next_stop=1;
		else next_stop=0;

		if ( ( stop  & ( ~strstop  ) ) | ( stopped  & ( ~( ( ~strstop  ) | ( 
			strstop  ) ) ) ) | ( stopped  & ( ~strstop  ) )) next_stopped=1;
		else next_stopped=0;

		if ( ( CLEAR  & ( 1'h1 ) ) | ( zero  & ( ~( ( strstop  ) | ( ~strstop  ) ) 
			) ) | ( zero  & ( ~strstop  ) )) next_zero=1;
		else next_zero=0;


		if ( ( counting  & ( ~( ( strstop  ) | ( ~strstop  ) ) ) ) | ( counting  & 
			( ~strstop  ) ) | ( start  & ( ~strstop  ) ) | ( start  & ( ~( ( ~strstop  ) 
			| ( strstop  ) ) ) ) | ( start  & ( strstop  ) ) | ( stopped  & ( strstop  ) 
			) | ( zero  & ( strstop  ) )) next_clkout=1;
		else next_clkout=0;

		if ( ( CLEAR  & ( ~( ( 1'h1 ) ) ) )) next_rst=1;
		else next_rst=0;
	end
endmodule