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V 的代码
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
sdram_test_tb.v
`timescale 1ns/1ns
module sdram_test_tb;
reg clk;
reg rst;
reg start_read;
initial begin
clk = 0;
rst = 0;
start_read = 0;
#100 rst = 1;
#1000 start_read = 1;
end
always #10 clk =
sdram_test_tb.v
`timescale 1ns/1ns
module sdram_test_tb;
reg clk;
reg rst;
reg start_read;
initial begin
clk = 0;
rst = 0;
start_read = 0;
#100 rst = 1;
#1000 start_read = 1;
end
always #10 clk =
mt48lc2m32b2.v
/****************************************************************************************
*
* File Name: MT48LC2M32B2.V
* Version: 1.0
* Date: March 13th, 2001
* Model
control_interface.v
/******************************************************************************
*
* LOGIC CORE: Control Interface - Top level module
* MODULE NAME: control_interface()
* COM
sdr_sdram.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller
* MODULE NAME: sdr_sdram()
* COMPANY: Northw
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
sdr_data_path.v
/******************************************************************************
*
* LOGIC CORE: SDR Data Path Module
* MODULE NAME: sdr_data_path()
* COMPANY: No
command.v
/******************************************************************************
*
* LOGIC CORE: Command module
* MODULE NAME: command()
* COMPANY: Northwest Logi
mt48lc8m16a2.v
/****************************************************************************************
*
* File Name: MT48LC8M16A2.V
* Version: 0.0f
* Date: July 8th, 1999
* Model: