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wrfifo_bb.v
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: wrfifo.v
// Megafu
pll_ctrl_inst.v
PLL_ctrl PLL_ctrl_inst (
.areset ( areset_sig ),
.inclk0 ( inclk0_sig ),
.c0 ( c0_sig ),
.c1 ( c1_sig ),
.e0 ( e0_sig ),
.locked ( locked_sig )
);
sdram_module.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company :
// Engineer :
// Create Date :
// Design Name :
// Module Name : sdram_mo
rdfifo_inst.v
rdfifo rdfifo_inst (
.data ( data_sig ),
.rdclk ( rdclk_sig ),
.rdreq ( rdreq_sig ),
.wrclk ( wrclk_sig ),
.wrreq ( wrreq_sig ),
.q ( q_sig ),
.wrusedw ( wrusedw_sig )
);
pll_ctrl_bb.v
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL_ctrl.v
// Me
uart_ctrl.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company :
// Engineer :
// Create Date :
// Design Name :
// Module Name : uart_ctr
wrfifo.v
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: wrfifo.v
// Megafuncti
sys_ctrl.v
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company :
// Engineer :
// Create Date :
// Design Name :
// Module Name : sys_ctrl
ddsqam.v
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation,
lcd_test.v
module lcd_test(clkin,DE,CLKOUT,HSYNC,YSYNC,PON,HL,JGND,DATA);
input clkin;
output DE,CLKOUT,HSYNC,YSYNC,PON,HL;
output [15:0]DATA;
output [7:0]JGND;
reg DE,CLKOUT,HSYNC,YSYNC,DEX,PON,TONG,HL;
r