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找到约 7,641 项符合
V 的代码
lcd.v
module lcd(sram_data,in_out_data,clk_in_data,clkin,OE,CE,WE,LB,UB,ADDER,DE,CLKOUT,HSYNC,YSYNC,PON,HL,JGND,DATA,led1,led2);
inout [15:0] sram_data;
input [15:0] in_out_data;
input clkin,clk_in_data;
testtry.v
module test(clk,rst,
data,addr,ba,
sdclk,cke,
cs_n,ras_n,cas_n,we_n,dqm,
flash_ce,flash_oe,flash_rw,
sram_ce,sram_oe,sram_we,sram_be,
data_out,led);
input
page_wr.v
module test(clk,rst,
data,addr,ba,
sdclk,cke,
cs_n,ras_n,cas_n,we_n,dqm,
flash_ce,flash_oe,flash_rw,
sram_ce,sram_oe,sram_we,sram_be
);
input clk,r
burst_wr.v
module test(clk,rst,
data,addr,ba,
sdclk,cke,
cs_n,ras_n,cas_n,we_n,dqm,
flash_ce,flash_oe,flash_rw,
sram_ce,sram_oe,sram_we,sram_be,
data_out,led);
input
testtry.v
module test(clk,rst,
data,addr,ba,
sdclk,cke,
cs_n,ras_n,cas_n,we_n,dqm,
flash_ce,flash_oe,flash_rw,
sram_ce,sram_oe,sram_we,sram_be,
data_out,led);
input
mt48lc2m32b2.v
/****************************************************************************************
*
* File Name: MT48LC2M32B2.V
* Version: 1.0
* Date: March 13th, 2001
* Model
control_interface.v
/******************************************************************************
*
* LOGIC CORE: Control Interface - Top level module
* MODULE NAME: control_interface()
* COM
sdr_sdram.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller
* MODULE NAME: sdr_sdram()
* COMPANY: Northw
params.v
/******************************************************************************
*
* LOGIC CORE: SDR SDRAM Controller - Global Constants
* MODULE NAME: params()
* COMPANY:
sdr_data_path.v
/******************************************************************************
*
* LOGIC CORE: SDR Data Path Module
* MODULE NAME: sdr_data_path()
* COMPANY: No