源码文件
Network Working Group G. Meyer Request for Comments: 1581 …
timing circuit 源代码
汇集 timing circuit 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
Network Working Group G. Meyer Request for Comments: 2091 …
源码文件
3 Way Active Loudspeaker eng 3-Way Active Loudspeaker
源码文件
MIXER 6+ channel in English Audio Modular MIXER with 6 and up input Channel &n…
源码文件
command line: ./testfifo_isim_beh.exe -intstyle ise -ipchost localhost -ipcport 2414 Tue Feb 03 15:56:…
源码文件
command line: ./test123_isim_beh.exe -intstyle ise -ipchost localhost -ipcport 1500 Wed Jan 21 18:11:3…
源码文件
the circuit diagram is same as the old DS1307 project. this software is still under construction. its just a beta version of the…
源码文件
// Test circuit for quantizer simulator lang=spectre ahdl_include "quantizer.vams" Vclk (clk 0) vsource type=pulse val1=1 perio…
源码文件
// Test circuit for quantizer simulator lang=spectre ahdl_include "quantizer.vams" Vclk (clk 0) vsource type=pulse val1=1 perio…
源码文件
edif2blif Version 1.00 June 30, 1998 Author: Paul Leventis (leventi@eecg.utoronto.ca) Web Page: **** Contents ^^^^^^^^ Author…