isim.log

verilog source code for uart design

 command line:
   ./testfifo_isim_beh.exe
     -intstyle  ise
     -ipchost  localhost
     -ipcport  2414

Tue Feb 03 15:56:16 2009

Total Line Count = 123

 Elaboration time 0.015625 sec.

 Estimate current memory usage 35.0454 Meg. 

 Total signals 18
 Total nets 21
 Total signal drivers 10
 Total blocks 3
 Total primitive blocks 2
 Total processes 11
ntrace select -o on -n /testfifo/data1 
ntrace select -o on -n /testfifo/full 
ntrace select -o on -n /testfifo/empty 
ntrace select -o on -n /testfifo/clk 
ntrace select -o on -n /testfifo/rd 
ntrace select -o on -n /testfifo/wr 
ntrace select -o on -n /testfifo/data 
ntrace start 
run 1000 ns 
Simulator is doing circuit initialization process.
Finished circuit initialization process.
run 10000 ns