源码文件
This directory contains all executables (or links) and scripts used for the conversion of edif files, and the optimization and pac…
timing circuit 源代码
汇集 timing circuit 相关的电路原理图、PCB工程文件、单片机/FPGA源代码、数据手册与应用设计方案。
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源码文件
#ifndef _NR4_H #define _NR4_H /* nr4.h: defines for netrom layer 4 (transport) support */ #ifndef _MBUF_H #include "mbuf.h"…
源码文件
/* * nr4subr.c: subroutines for net/rom transport layer. */ #include #include "global.h" #include "mbuf.h" #include "…
源码文件
% Matlab M-file for Exercise 1 of text. % It plots the Simulation results of the vco circuit % in Fig. 2.4 of the text. Labels…
源码文件
Theory behind calculation of Voltage divider circuit. All we want is input voltage to ADC should not increase 5V and Our maximu…
源码文件
command line: dfgf_isim_par.exe -sdfmax digital_clk_timesim.sdf -sdfroot /UUT -tclbatch isim.cmd -l…
源码文件
command line: test_pwm_sch_isim_beh.exe -tclbatch isim.cmd -log test_pwm_sch.isim_beh_log -intstyle ise …
源码文件
command line: test_mag4comp_v_isim_beh.exe -tclbatch isim.cmd -log test_mag4comp_v.isim_beh_log -intstyle …
源码文件
command line: test_cntr4_isim_beh.exe -tclbatch isim.cmd -log test_cntr4.isim_beh_log -intstyle ise …
源码文件
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