软件开发人员必备工具书，，目录如下Welcome to Software Construction [1]1.1 What Is Software Construction?1.2 Why Is Software Construction Important?1.3 How to Read This Book......7.1 Valid Reasons to Create a Routine7.2 Design at the Routine Level7.3 Good Routine Names7.4 How Long Can a Routine Be?7.5 How to Use Routine Parameters7.6 Special Considerations in the Use of Functions7.7 Macro Routines and Inline RoutinesDefensive Programming [5.6 + new material]8.1 Protecting Your Program From Invalid Inputs8.2 Assertions8.3 Error Handling Techniques8.4 Exceptions8.5 Barricade Your Program to Contain the Damage Caused by Errors8.6 Debugging Aids8.7 Determining How Much Defensive Programming to Leave in Production Code8.8 Being Defensive About Defensive ProgrammingThe Pseudocode Programming Process [4+new material]9.1 Summary of Steps in Building Classes and Routines9.2 Pseudocode for Pros9.3 Constructing Routines Using the PPP9.4 Alternatives to the PPP......
上传时间： 2021-12-08
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FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
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基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
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1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
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上传时间： 2022-01-09
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Extensively rewritten to present the C++11 language, standard library, and key design techniques as an integrated whole, Stroustrup thoroughly addresses changes that make C++11 feel like a whole new language, offering definitive guidance for leveraging its improvements in performance, reliability, and clarity. C++ programmers around the world recognize Bjarne Stoustrup as the go-to expert for the absolutely authoritative and exceptionally useful information they need to write outstanding C++ programs. Now, as C++11 compilers arrive and development organizations migrate to the new standard, they know exactly where to turn once more: Stoustrup's C++ Programming Language, Fourth Edition.Bjarne Stroustrup是C++的设计师和最早的实现者，也是《C++程序设计语言》、《带标注的C++参考手册》和《C++语言的设计与演化》的作者。他从丹麦Aarhus大学和英国牛津大学毕业，现在是AT&T大规模程序设计研究部的负责人，AT&T特别成员，AT&T贝尔实验室特别成员，以及ACM特别成员。Stroustrup的研究兴趣包括分布式系统、操作系统、模拟、设计和程序设计。他也是Addison·Wesley的C++In-Depth系列书籍的编辑。
标签： C++
上传时间： 2022-02-01
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verilog实现I2C通信的slave模块源码状态机设位计可做I2C接口的仿真模型//`timescale 1ns/1psmodule I2C_slv (input [6:0] slv_id,input RESET,input scl_i, //I2C clkinput sda_i, //I2C data ininput [7:0] I2C_RDDATA,////////////////////////output reg sda_o, //I2C data outoutput reg reg_w, //reg write enable pulse (1T of scl_i)output reg [7:0] I2C_ADDR,output reg [7:0] I2C_DATA); parameter ST_ADDR = 4'd0; parameter ST_ACK = 4'd1; parameter ST_WDATA1 = 4'd2; parameter ST_WACK1 = 4'd3; parameter ST_WDATA2 = 4'd4; parameter ST_WACK2 = 4'd5; parameter ST_WDATA3 = 4'd6; parameter ST_WACK3 = 4'd7; parameter ST_RDATA1 = 4'd8; parameter ST_RACK1 = 4'd9; parameter ST_IDLE = 4'd15;//---------------------------------------------------------------------------// Signal Declaration//--------------------------------------------------------------------------- reg i2c_start_n, i2c_stop_n; //wire RESET_scl; wire i2c_stp_n, i2c_RESET; reg [3:0] i2c_cs, i2c_ns; reg [3:0] cnt_bit; reg [7:0] d_vec; reg i2c_rd, i2c_ack; reg [7:0] I2C_RDDATA_latch;
上传时间： 2022-02-03
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Proprietary Code Read Out Protection (PCROP) ----- 专有代码读取保护 现在产品开发过程中，二次开发将会越来越多，设计公司开发出自己产品后交给终端客户进行二次功能或补充开发，简称二次开发，设计公司某些程序代码不希望公开给终端客户，但同时又希望部分函 数功能可以给终端客户使用，这时就需要有一种专有代码保护机制供客户使用，STM32F4xx 芯片中的 PCROP 可以解决类似问题。
标签： stm32
上传时间： 2022-02-21
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This Getting Started Guide is written for Maxwell beginners and experienced users who would like to quickly re familiarize themselves with the capabilities of MaxwelL.This guide leads you step-by-step through solving and analyzing the results of a rotational actuator magnetostatic problem with motion By following the steps in this guide, you will learn how to perform the following tasks Modify a models design parameters y Assign variables to a model's design parameters.Specify solution settings for a design Validate a designs setupRun a maxwell simulation v Plot the magnetic flux density vecto v Include motion in the simulation本《入门指南》是为希望快速重新熟悉MaxwelL功能的Maxwell初学者和有经验的用户编写的。本指南将引导您逐步解决和分析旋转致动器静运动问题的结果。按照本指南中的步骤，您将学习如何执行以下任务。修改模型设计参数y将变量分配给模型的设计参数。指定设计的解决方案设置验证设计设置运行maxwell模拟v绘制磁通密度vecto v在模拟中包含运动
上传时间： 2022-03-10
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本文主要介绍如何在Wado设计套件中进行时序约束，原文出自 xilinx中文社区。1 Timing Constraints in Vivado-UCF to xdcVivado软件相比于sE的一大转变就是约束文件，5E软件支持的是UcF（User Constraints file，而 Vivado软件转换到了XDc（Xilinx Design Constraints）。XDC主要基于SDc（Synopsys Design Constraints）标准，另外集成了Xinx的一些约束标准可以说这一转变是xinx向业界标准的靠拢。Altera从 TimeQuest开始就一直使用SDc标准，这一改变，相信对于很多工程师来说是好事，两个平台之间的转换会更加容易些。首先看一下业界标准SDc的原文介绍：Synopsys widely-used design constraints format, known as sDc, describes the design intent"and surrounding constraints for synthesis, clocking, timing, power, test and environmental and operating conditions. sDc has been in use and evolving for more than 20 years, making it the most popular and proven format for describing design constraints. Essentially all synthesized designs use SDc and numerous EDa companies have translators that can read and process sDc
标签： vivado
上传时间： 2022-03-26
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因此，您想编写一个内核模块。您知道C，您已经编写了一些可以作为进程运行的常规程序，现在您想知道真正的动作在哪里，一个通配指针可以擦掉文件系统，核心转储意味着重新启动。内核模块到底是什么？模块是可以根据需要加载和卸载的代码段。它们扩展了内核的功能，而无需重新引导系统。例如。模块驱动程序的一种类型是设备驱动程序，它允许内核访问没有模块的系统硬件，我们将不得不构建单片内核并将新功能直接添加到内核映像中，除了具有更大的内核之外，这还具有缺点每次我们想要新功能时都要求我们重建并重新启动内核的过程So, you want to write a kernel module. You know C, you, ve written a few normal programs to run as processes, and now you want to get to where the real action is, to where a single wild pointer can wipe out your file system and a core dump means a reboot.What exactly is a kernel module? Modules are pieces of code that can be loaded and unloaded into th upon demand. They extend the functionality of the kernel without the need to reboot the system. For example.one type of module is the device driver, which allows the kernel to access hardware connected to the syste without modules, we would have to build monolithic kernels and add new functionality directly into the em ernel image, Besides having larger kernels
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上传时间： 2022-03-30
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