FPGA读写SD卡读取BMP图片通过LCD显示例程实验 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 实验简介在前面的实验中我们练习了 SD 卡读写，VGA 视频显示等例程，本实验将 SD 卡里的 BMP 图片读出，写入到外部存储器，再通过 VGA、LCD 等显示。本实验如果通过液晶屏显示，需要有液晶屏模块。2 实验原理在前面的实验中我们在 VGA、LCD 上显示的是彩条，是 FPGA 内部产生的数据，本实验将彩条替换为 SD 内的 BMP 图片数据，但是 SD 卡读取速度远远不能满足显示速度的要求，只能先写入外部高速 RAM，再读出后给视频时序模块显示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
标签： fpga
上传时间： 2021-10-27
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Multisim官方示例Multisim仿真例程基础电路范例135例合集:Chapter 1 - RLC CircuitsChapter 2 - DiodesChapter 3 - TransistorsChapter 4 - AmplifiersChapter 5 - OpampsChapter 6 - FiltersChapter 7 - Miscellaneous CircuitsFundamental Circuits.pdf004 Parallel DC Circuits.ms10005 Series-Parrallel DC Circuit.ms10006 Current Analysis.ms10007 Millmans Theorem 1.ms10008 Millmans Theorem 2.ms10009 Kirchhoff's Current Law.ms10010 Thevenin's Theorem.ms10011 Superposition Principle.ms10012 Nortons Theorem and Source Conversion.ms10013 AC Voltage Measurement.ms10014 Frequency Response of the Series RL Network.ms10015 RL High and Low Pass Filter.ms10016 Frequency Response of the Series RC Network.ms10017 RC High and Low Pass Filter.ms10019 Center-Tapped Full-Wave Rectifier.ms10020 Bridge Rectifier.ms10021 Capacitor-Input Rectifier Filter.ms10022 Diode Clipper (Limiter).ms10023 Diode Clipper.ms10024 Diode Clamper (DC Restorer).ms10025 Diode Voltage Doubler.ms10026 Zener Diode and Voltage Regulation 1.ms10027 Zener Diode and Voltage Regulation 2.ms10028 Zener Diode and Voltage Regulation 3.ms10105 TTL Inverter.ms10107 TTL Gate.ms10109 OR Gate Circuit.ms10111 Over-Damp Circuit.ms10113 Critical-Damp Circuit.ms10115 Series RLC Circuit 1.ms10117 Clapp Oscillator.ms10119 Differential Amplifier 1.ms10121 Differential Amplifier in Common Mode.ms10123 LC Oscillator with Unity Gain Buffer.ms10125 Notch Filter.ms10127 PNP Differential Pair.ms10129 Crossover Network.ms10131 Second-Order High-Pass Chebyshev Filter.ms10133 Third-Order High-Pass Chebyshev Filter.ms10135 Fifth-Order High-Pass Filter.ms10
标签： multisim
上传时间： 2021-10-27
上传用户：trh505
国外大牛写的电源控制仿真模型，讲解很详细。
标签： 电源控制仿真模型
上传时间： 2021-11-03
上传用户：kent
基于cubeMX的stm32L0系列单片机RTC配置及相关寄存器配置代码，可用于低功耗模式下（stop mode）对单片机进行唤醒，无需外部唤醒源，只需配置RTC的内部唤醒功能即可实现，代码亲测可用。
上传时间： 2021-11-16
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USB_MICRO USB_MNI USB扁口座 TF卡槽 SOIC8 LQFP32芯片ALTIUM 库（3D PCB封装库）, 3D封装，已在项目中使用，可以做为你的设计参考。详细列表如下：Component Count : 94Component Name-----------------------------------------------32165032-8MHZAMS1117ANT2AntennaBATbuzzerCapCAP-0805CAP-3216CD32Crystal Oscillator 3225HC-06KEY-2PINLED-0603LQFP-100LQFP32LQFP44LQFP44 10X10_LLQFP44 10X10_MLQFP44 10X10_NLQFP48LQFP48 7X7_LLQFP48 7X7_MLQFP48 7X7_NLQFP64 10x10_LLQFP64 10x10_MLQFP64 10x10_NMagMOTONRF24L01NRF24L01-modeOLED-0.96-PIN7QFN20_4X4QFN24_4X4QFN32_5X5remoteRES-0603RFX2401CRPSG90SH1.0mm-4PINSH1.0MM-5PINSH1.0mm-6PINSMA-ANTSMA/DO-214SOIC-8SOP16SOT-23-3SOT-23-5SOT-89SOT-223SPL06-001STM32F030C8T6STM32F030F4P6STM32F103C8T6straight-1x2pinstraight-1x2pin - duplicatestraight-1x2pin - duplicate1straight-1x3pinstraight-1x3pin - duplicatestraight-1x3pin - duplicate1straight-1x4pinstraight-1x4pin - duplicatestraight-1x5pinstraight-1x8pinstraight-1x8pin - duplicatestraight-2x2pinstraight-2x3pinstraight-2x4pinstraight-2x5pinSW-NO/OFF-PIN3SW-SMD1SW-SMD2SWITCH-DIP-6*6*7SX1308TF-CARDTO-263-5TP4056USBUSB_MICROUSB_MNI_BUSB-MICRO-1winding_1x2pinwinding_1x3pinwinding_1x4pinwinding_1x5pinwinding_1x8pinwinding_2x2pinwinding_2x3pinwinding_2x4pinwinding_2x5pinXTAL-5070/SMDXTAL-QC49/SMD
标签： usb
上传时间： 2021-12-02
上传用户：aben
NCP1399 是高性能电流模式控制器，半桥谐 变换器。此控制器实现 600 V 门驱动、 简化布 局和减少外部组件计数 。built - in 和 Brown - Out 输入函数简化了执行在所有应用程序的控制器。 在 PFC 前阶段的应用 NCP1399 需要设有专用的 输出驱动 PFC 前级控制器。此功能专用 skip-mode 技术进一步提高轻负载效率的整个应 用程序。 NCP1399 提供全套的保护功能允许安全 运行在任何应用程序中。这包括：过载保护，过 流保护以防止硬开关周期， brown- out 检测，打 开光电耦合器检测， 死区自动调整， 过电压（OVP） 和 (OTP) 过温保护
上传时间： 2021-12-17
上传用户：qingfengchizhu
HI3520DV400全套资料（Cadence arregro原理图+PCB+bom+镜像软件），1个HDMI输入，1个HDMI输出，1个3.5音频输入，1个3.5音频输出。2GB-DDR3，2个USB2.0,1个LAN，已经调试通过，固件都已经打包好。拿来就可以打板生产，包括原理图，PCB，u-boot,kernel,rootfs。
标签： hi3520dv400 cadence arregro
上传时间： 2021-12-28
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1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
标签： DDR4
上传时间： 2022-01-09
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瑞芯微RK3399 软件件设计资料 RK3399 Linux Debian软件开发文档资料,SDK 是基于 Linux 64bit 系统，内核基于 kernel 4.40，适用于 RK3399 挖掘机以及基于其 上所有 linux 开发产品。 支持 VPU 硬解码、GPU 3D、QT 等功能。具体功能调试和接口说明
上传时间： 2022-01-29
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瑞芯微RK3399 软硬件资料包括3款硬件Cadence原理图PCB文件，硬件设计文档，LINIUX软件开发文档i资料硬件文档主要介绍RK3399处理器硬件设计的要点及注意事项，旨在帮助RK客户缩短产品的设计周期、提高产品的设计稳定性及降低故障率。请客户参考本指南的要求进行硬件设计，同时尽量使用RK发布的相关核心模板。 SDK 是基于 Linux 64bit 系统，内核基于 kernel 4.40，适用于 RK3399 挖掘机以及基于其 上所有 linux 开发产品。 支持 VPU 硬解码、GPU 3D、QT 等功能。具体功能调试和接口说明，请阅读工程目录 docs/目录下文档。
上传时间： 2022-01-29
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