使用主流buck降压芯片设计双轨电源Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator
标签： 电源
上传时间： 2021-11-07
上传用户：20125101110
LAN9254 + SAME54 MCU 从站设计•1.支持2/3个port口的EtherCat Slave控制器，并内置有8个FMMU 和8个SyncManagers; 并有8KB的更大的DPRAM存储资源；•2. 8/16bit总线，支持和大多数8/16bit以及32bit的host MCU通讯； •3. 内部集成了支持HP Auto-MDIX的以太网PHY芯片； •4. 支持Wake on Lan以太网远程唤醒技术；兼容EtherCat P协议； •5. 具有低功耗工作模式，可以允许系统进入睡眠模式以节省更多功耗，直到被Master访问； •6. 支持线缆诊断技术； •7. 支持1.8V~3.3V的灵活可变的IO电压，省去需要外加Voltage shifter芯片的成本； •8. 多功能GPIO，可以配置为Local Bus，SPI, PWM，通用GPIO等多种接口功能； •9. 工业级温度范围，最高可以支持105度工业温度要求；
标签： mcu lan9254 ethercat从站
上传时间： 2021-11-09
上传用户：
AT89S52单片机主8入8出继电器工控主板ALTIUM设计硬件原理图+PCB文件,2层板设计，大小为121x149mm，Altium Designer 设计的工程文件，包括完整的原理图及PCB文件，可以用Altium(AD)软件打开或修改，可作为你的产品设计的参考。主要器件型号列表如下：Library Component Count : 25Name Description----------------------------------------------------------------------------------------------------24LC02AJKG 按键开关AT89S52-P 8 位微处理器/40引脚CAP CapacitorCAPACITOR POL CapacitorCPDR 瓷片电容CRYSTAL CrystalD Connector 9 Receptacle Assembly, 9 Position, Right AngleDG 电感DJDR 电解电容GO 光耦Header 5X2 Header, 5-Pin, Dual rowJDQYCK 继电器——1常开1常闭LED 发光二极管LM2576HVT-3.3 Simple Switcher 3A Step Down Voltage RegulatorMAX232 NPN NPN Bipolar TransistorPZ_2 排针——2PZ_3 排针——3RES2Res 电阻Res PZ_8 8位排阻SW-DPST Double-Pole, Single-Throw SwitchWY2JG 稳压二级管ZL2JG 整流二极管
上传时间： 2021-11-17
上传用户：kingwide
BTS7960大功率直流电机驱动板ALTIUM设计硬件原理图+PCB文件,2层板设计，大小为66*76mm, 包括完整的原理图和PCB工程文件，可以做为你的设计参考。主要器件如下：Library Component Count : 13Name Description----------------------------------------------------------------------------------------------------CPDR 瓷片电容Component_1_1 DG 电感DJDR 电解电容Header 2 Header, 2-PinLED 发光二极管LED3 Typical BLUE SiC LEDLM2576HVT-3.3 Simple Switcher 3A Step Down Voltage RegulatorPZ_2 排针——2RES2 Res 电阻TLP521-1WY2JG 稳压二级管
上传时间： 2021-11-21
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AC220V转DC(12V15W )电源板AD设计硬件原理图+PCB文件，2层板设计，大小为100*55mm, ALTIUM设计的原理图+PCB文件，可以做为你的学习设计参考。主要器件型号如下：Library Component Count : 24Name Description----------------------------------------------------------------------------------------------------2N3904 NPN General Purpose Amplifier2N3906 PNP General Purpose AmplifierBRIDGE1 Diode BridgeCON2 ConnectorCap CapacitorCap Pol1 Polarized Capacitor (Radial)D Zener Zener DiodeDIODE Diode 1N914 High Conductance Fast DiodeECELECTRO2 Electrolytic CapacitorFP103 FUSE-HHeader 2 Header, 2-PinINDUCTOR2 NMOS-2 N-Channel Power MOSFETPC837 OptoisolatorRES2-B Res Varistor Varistor (Voltage-Sensitive Resistor)T TR-2B TRANS1UCC28051 Volt Reg Voltage Regulator
上传时间： 2021-11-21
上传用户：kent
ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
标签： 隔离
上传时间： 2021-11-24
上传用户：kingwide
General Design Specification:1. AC Input Range 180-264Vac, Isolated ac-dc offline, 12LEDS,Output 700mA2. Intelligent wall dimmer detections(Leading-edge dimmer , Trailing-edgedimmer , No-dimmer)3. Multiple dimming control scheme4. Wide dimming range from 1% up to 100%5. No visible flicker6. Resonant control to achieve high efficiency7. High Power Factor, 0.9 without dimmer8. Temperature degrade control to adjust the LED9. Primary-only Sensing eliminates opto-isolator feedback and simplifies design
标签： iw3617
上传时间： 2021-12-03
上传用户：canderile
The PC1099N from Pixelplus is a CMOS Image Sensor with Mega Pixels 0.3 MP, VGA, Supply Voltage Analog: 3.3 V, HVDD: 3.3 V, CVDD: 3.3 V, Frame Rate 50 to 60 fps, Dynamic Range 63.2 dB, SNR 45.3 dB. More details for PC1099N can be seen below.
标签： pc1099n
上传时间： 2021-12-12
上传用户：qingfengchizhu
FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
上传用户：
基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上传时间： 2021-12-18
上传用户：
